A methodology for vertical Reuse of functional verification from subsystem to SoC level with seamless SoC emulation

Verifying a complex SoC is challenging. The testbench and testcases must be developed early as these are used for everything from SoC verification to achieve higher coverage on features/protocol coverage, i/f integration and performance verification. Time to market makes early software development a necessity. Verification assisted with early software development needs more than dynamic simulation and emulation methodology comes to rescue. Firstly, the verification of RTL in subsystem environment has been efficient with a SV/UVM methodology which focus on Reuse on testbench and testcases along with the verification environment around Verification IP. The Reuse methodology in center, the emulation methodology offers a huge theoretical performance advantage over dynamic simulations. Theoretically, too often verification teams get bogged down spending enormous amounts of time porting verification infrastructure from one level of testing to the next. It is prone to testbench bugs also. Beyond the horizontal and vertical re-use model, there is a need of end to end re-use across the design and verification flow. This paper explains a generic methodology to achieve this end-to-end reuse in an ongoing project. Keywords—functional verification, emulation, SV/UVM, Lightweight virtual platform, LVP, dynamic simulation, subsystem verification, SoC verification, early software development, system level verification